• DocumentCode
    979091
  • Title

    Below 20 ps/gate operation with GaAs SAINT FETs at room temperature

  • Author

    Yamasaki, Kazuhiko ; Yamane, Y. ; Kurumada, K.

  • Author_Institution
    NTT, Musashino Electrical Communication Laboratory, Musashino, Japan
  • Volume
    18
  • Issue
    14
  • fYear
    1982
  • Firstpage
    592
  • Lastpage
    593
  • Abstract
    Room-temperature ring oscillation at 19.6 ps/gate has been accomplished with SAINT FETs using bulk GaAs and implantation. These results have been obtained along with extrinsic resistance reduction and capacitance reduction by taking full advantage of the n+-gate spacing controllability.
  • Keywords
    III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated circuit technology; integrated logic circuits; 19.6 ps/gate; GaAs SAINT FETs; MESFET; capacitance reduction; extrinsic resistance reduction; field effect integrated circuits; implantation; n+-gate spacing controllability; ring oscillation; room temperature; self aligned implantation for n+-layer technology;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19820406
  • Filename
    4246544
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=979091