On wafer-packing problems

Author

Du, David H C ; Lin, Ichiang ; Chang, K.C.

Author_Institution

Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA

Volume

42

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

1382

Lastpage

1388

Abstract

Wafer packing is a process of combining multiple chip designs on the same wafer such that the fabrication cost can be shared by several designs and hence reduced. This technique is widely used for designs that require a small number of dies or chips. It is essential to have computer algorithms to decide how to allocate designs to wafers in order to reduce the total fabrication cost. Based on different wafer fabrication techniques, two versions of the wafer packing problem are formulated. The authors study different variations for each version. They present algorithms to find optimal solutions for these variations which are polynomial-time solvable. They also present heuristic algorithms for those proven to be NP-hard. The effectiveness of the proposed algorithms is demonstrated by experimental results

Keywords

VLSI; multichip modules; NP-hard; VLSI design; fabrication cost; heuristic algorithms; multiple chip designs; polynomial-time solvable; wafer-packing problems; Chip scale packaging; Circuit testing; Computer science; Costs; Electron beams; Electron optics; Fabrication; Lithography; Manufacturing processes; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.247840

Filename

247840