Title :
Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device
Author :
Cao, Yuhan ; Ning, Wenguo ; Le Luo
Author_Institution :
State Key Labs. of Transducer Technol., Chinese Acad. of Sci. (CAS), Shanghai, China
fDate :
7/1/2009 12:00:00 AM
Abstract :
In this paper, a wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device such as resonator is presented. Wet etching technique combined with dry etching technique is utilized to achieve a ldquoY-shapedrdquo through wafer interconnection structure to shorten the TSV in order to reduce cost. Ansoft HFSSTM 3-D electromagnetic simulator is used to assess the transition properties of signal with frequency of the new interconnection structure. Sn solder bonding is utilized to achieve simultaneous TSV connection and cavity hermetic sealing. Average shear strength of 19.5 Mpa and excellent leak rate of around 1.9 times 10-9 atm cc/s have been achieved, which meet the requirements of MIL-STD-883E. Kevin structure is also fabricated to measure the resistance of the metallized TSV, the resistance of the ldquoY-shapedrdquo through wafer interconnection and the contact resistance of the Cu/Sn IMC bond joint.
Keywords :
copper alloys; elemental semiconductors; etching; hermetic seals; integrated circuit interconnections; micromechanical devices; micromechanical resonators; silicon; soldering; tin alloys; wafer level packaging; CuSn; Kevin structure; MEMS device; Si; average shear strength; cavity hermetic sealing; contact resistance; dry etching technique; electromagnetic simulator; low-temperature solder bonding; microelectromechanical system device; resonator; simultaneous TSV connection; simultaneous through silicon via connection; wafer interconnection structure; wafer-level package; wet etching technique; Combined dry and wet etching; Sn solder bonding; hermeticity; through silicon via (TSV); wafer-level packaging;
Journal_Title :
Electronics Packaging Manufacturing, IEEE Transactions on
DOI :
10.1109/TEPM.2009.2021766