Power-Aware Design of Nanometer MCML Tapered Buffers

A strategy to design MOS current-mode logic (MCML) tapered buffers is discussed. Closed-form expressions of the speed and the power consumption of MCML tapered buffers are first derived. Then, analytical criteria are presented to explore the power-delay design space and properly size the number of stages and the current tapering factor under a speed/power constraint. These criteria incorporate deep-submicron effects and are simple enough to be used in pencil-and-paper calculations. Being general and independent of the process adopted, the proposed design strategy allows for gaining an insight into the interdependence of design parameters, technology parameters and performance. Moreover, the proposed models of the delay/power consumption under assigned constraints allow the designer to predict the achievable performance before actually carrying out the design. Results are validated by means of Spectre simulations on a 90-nm CMOS technology.