Quantifying the Reduction in Collected Charge and Soft Errors in the Presence of Guard Rings

Author

Narasimham, Balaji ; Shuler, Robert L. ; Black, Jeffrey D. ; Bhuva, Bharat L. ; Schrimpf, Ronald D. ; Witulski, Arthur F. ; Holman, William Timothy ; Massengill, Lloyd W.

Author_Institution

Vanderbilt Univ., Nashville

Volume

8

Issue

1

fYear

2008

fDate

3/1/2008 12:00:00 AM

Firstpage

203

Lastpage

209

Abstract

Soft errors pose a major reliability threat to advanced electronic components and systems. Novel techniques are needed to mitigate the soft-error rate (SER) of integrated circuits (ICs), and in some cases, a combination of different mitigation techniques may be required for significant performance improvements. In this paper, an autonomous single-event-transient (SET) pulse-width characterization technique is used to quantify the effect of hardened-by-design structures, such as guard rings (GRs), in reducing the collected charge and SER of ICs. Experimental results obtained for a 0.35-mum technology show a reduced SET pulse-width for devices with GRs; the corresponding reduction in SER was estimated to be greater than 55% for technologies ranging from 0.35 mum to 70 nm.

Keywords

integrated circuit reliability; charge collection; different mitigation techniques; guard rings; integrated circuits; single event transient; single-event-transient pulse-width characterization technique; soft-error rate; Collected charge; RHBD; SE transient (SET); SER; SET; Terms Single event; collected charge; guard rings; guard rings (GRs); pulse-width; pulsewidth; radiation hardening by design (RHBD); single event (SE); single event transient; soft error; soft-error rate (SER);

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2007.912778

Filename

4384602