Quantifying the Reduction in Collected Charge and Soft Errors in the Presence of Guard Rings

Soft errors pose a major reliability threat to advanced electronic components and systems. Novel techniques are needed to mitigate the soft-error rate (SER) of integrated circuits (ICs), and in some cases, a combination of different mitigation techniques may be required for significant performance improvements. In this paper, an autonomous single-event-transient (SET) pulse-width characterization technique is used to quantify the effect of hardened-by-design structures, such as guard rings (GRs), in reducing the collected charge and SER of ICs. Experimental results obtained for a 0.35-mum technology show a reduced SET pulse-width for devices with GRs; the corresponding reduction in SER was estimated to be greater than 55% for technologies ranging from 0.35 mum to 70 nm.