Design of a performance enhanced traceback algorithm for the Viterbi decoder

The authors propose an efficient traceback scheme for the parallel hardware implementation of the Viterbi algorithm. Compared to the conventional Viterbi algorithm, where output is selected arbitrarily when multiple survivor paths exist, the proposed algorithm decides decoding output by analysing the survivor paths of consecutive tracebacks. Experimental results show that the proposed algorithm exhibits improved error-correction capability compared to the existing algorithms