Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes

Author

Brea, V.M. ; Vilariño, David L. ; Paasio, Ari ; Cabello, Diego

Author_Institution

Dept. of Electron. & Comput. Sci., Univ. of Santiago de Compostela, Spain

Volume

51

Issue

5

fYear

2004

fDate

5/1/2004 12:00:00 AM

Firstpage

997

Lastpage

1013

Abstract

This paper introduces the processing core of a full-custom mixed-signal CMOS chip intended for an active-contour-based technique, the so-called pixel-level snakes (PLS). Among the different parameters to optimize on the top-down design flow our methodology is focused on area. This approach results in a single-instruction-multiple-data chip implemented by a discrete-time cellular neural network with a correspondence between pixel and processing element. This is the first prototype for PLS; an integrated circuit with a 9×9 resolution manufactured in a 0.25 -μm CMOS STMicroelectronics technology process. Awaiting for experimental results, HSPICE simulations prove the validity of the approach introduced here.

Keywords

CMOS integrated circuits; application specific integrated circuits; cellular neural nets; image segmentation; mixed analogue-digital integrated circuits; ASIC; CMOS STMicroelectronics technology process; HSPICE simulations; cellular neural network; mixed-signal CMOS DTCNN chip; pixel-level snakes; processing core design; CMOS integrated circuits; CMOS process; CMOS technology; Cellular neural networks; Design methodology; Design optimization; Integrated circuit manufacture; Manufacturing processes; Process design; Prototypes; ASIC; Active contours; CNN; CNN robustness; DTCNN; PLS; application-specific integrated circuit; cellular neural network; discrete-time CNN; mixed-signal design; pixel-level snakes;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2004.827625

Filename

1296811