Compact Modeling of Junction Current in Dynamically Depleted SOI MOSFETs

We report the compact modeling of junction current in dynamically depleted silicon-on-insulator (SOI) MOSFETs. The body-to-source built-in barrier lowering is obtained from the coupled surface potential equations which serve as the basis of surface-potential-based SOI MOSFET models. This barrier lowering is then incorporated into the advanced junction model to enable the unification of junction current in partially depleted and fully depleted SOI MOSFET models. Compared with 2-D TCAD simulations, the characteristics of body-to-source/drain junction current in dynamically depleted SOI MOSFETs are faithfully reproduced by the new approach.