A flexible bit-pattern associative router for interconnection networks

Author

Summerville, Douglas H. ; Delgado-Frias, José G. ; Vassiliadis, Stamatis

Author_Institution

Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA

Volume

7

Issue

5

fYear

1996

fDate

5/1/1996 12:00:00 AM

Firstpage

477

Lastpage

485

Abstract

A programmable associative approach to execute implicit routing algorithms is presented. Algorithms are mapped onto a set of bit-patterns that are matched in parallel. We have studied and mapped a large number of routing algorithms for a wide range of interconnection network topologies. Here we report three cases that illustrate the capabilities of the router scheme. For the studied topologies, the number of required bit-patterns is of the same order as the topology degree. The proposed approach is one of the fastest routers and requires a very small amount of hardware

Keywords

content-addressable storage; multiprocessor interconnection networks; network routing; adaptive routing; associative memories; associative router; flexible bit-pattern; flexible routers; interconnection network topologies; interconnection networks; oblivious routing; parallel; routing algorithm execution; Associative memory; Decoding; Delay; Hardware; Multiprocessor interconnection networks; Network topology; Routing; Senior members; Table lookup; Throughput;

fLanguage

English

Journal_Title

Parallel and Distributed Systems, IEEE Transactions on

Publisher

ieee

ISSN

1045-9219

Type

jour

DOI

10.1109/71.503772

Filename

503772