Title :
SEU reliability analysis of advanced deep-submicron transistors
Author :
Jain, P. ; Vasi, J. ; Lal, R.K.
Author_Institution :
Dept. of Electr. Eng., IIT Bombay, India
fDate :
6/1/2005 12:00:00 AM
Abstract :
A systematic evaluation of the single-event-upset (SEU) reliability of the advanced technologies-high-/spl kappa/ gate dielectric, elevated source-drain (E-SD), and lateral asymmetric channel (LAC) MOSFETs is presented for the first time in this work. Our simulations results gives a clear view of how the short channel effects in a device governs its SEU reliability and how this reasoning evolves at the circuit level. It is shown that devices with worsened short-channel effects (high-/spl kappa/ gate dielectric transistors) have a significantly reduced SEU-reliability in contrast to the devices with controlled short-channel effects (LAC and E-SD) or even a conventional device.
Keywords :
MOSFET; high-temperature electronics; radiation effects; reliability; MOSFET; SEU reliability analysis; SRAM; advanced deep-submicron transistors; charge enhancement; elevated source-drain; high-K gate dielectric transistors; lateral asymmetric channel; short-channel effects; single-event-upset; Circuit simulation; Dielectric devices; Los Angeles Council; MOSFETs; Materials reliability; Protons; Random access memory; Single event upset; Space technology; Transistors; SRAM; charge enhancement; elevated source-drain; high-; lateral asymmetric channel (LAC); scaling; short channel effects; single event upset (SEU);
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2005.848325
