Post-processing of clock trees via wiresizing and buffering for robust design

Achieving near-zero skew for a large clock tree is generally at the expense of adding large amounts of metal interconnect. This added metal can significantly increase the total clock-net capacitance, thereby increasing the power dissipation in proportion. In addition, it is shown that it becomes increasingly difficult to control clock-signal skew due to metal-wiring process variations as the total clock-net capacitance increases. In this paper we demonstrate that buffer insertion can be used to reduce the total capacitance, hence the power, while generating a design which is as robust as one with no intermediate buffering. Moreover, delays are reduced substantially as well. Given an initial feasible route with constraints. On wire widths, wire sizing and buffer insertion are performed concurrently at each iteration of optimal buffer location search. Statistical process variations of the buffers, their loads, and the metal interconnect parameters are considered as part of the robust design process