• DocumentCode
    984462
  • Title

    Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations

  • Author

    Xie, Lin ; Davoodi, Azadeh

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI
  • Volume
    27
  • Issue
    12
  • fYear
    2008
  • Firstpage
    2264
  • Lastpage
    2276
  • Abstract
    This paper illustrates the application of a novel theory, namely, the distributional robustness theory (DRT), to compute the worst-case timing yield of a circuit. The assumption is that the probability distributions of the process variables are unknown, and only their intervals and their ldquoclassrdquo of distributions are available. This paper considers practical classes to describe potential distributions which match with partial statistical information that might be available. Some classes are suitable for independent distributions that have symmetrical or asymmetrical shapes, while others can account for correlations. These classes have high flexibility to include various shapes of the distributions of the process variations. At a higher level, they can also capture the case when uncertainty in their correlation coefficients exists. The contributions of this paper are on formulating the DRT for different cases of variations and in deriving conditions (e.g., acceptable bounds on timing constraint, acceptable intervals of variations) that allow applying the results of the DRT. Compared with other recent works, the presented approach can include correlations among process variations and does not require knowledge of the exact function form of their joint distribution function. The presented approach is also applicable to other types of parametric yield.
  • Keywords
    integrated circuit design; integrated circuit yield; statistical distributions; statistical process control; distributional robustness theory; joint distribution function; partial statistical information; probability distributions; process variations; timing yield; Delay estimation; Distributed computing; Integrated circuit yield; Log-normal distribution; Probability distribution; Robustness; Shape; Timing; Uncertainty; Yield estimation; Class of distributions; convexity; correlations; robust estimation; timing yield; within-die (WID) and die-to-die (D2D) variations;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2008.2006146
  • Filename
    4670067