Low power design of DCT and IDCT for low bit rate video codecs

Author

August, Nathaniel J. ; Ha, Dong Sam

Author_Institution

Bradley Dept. of Electr. & Comput. Eng., State Univ., Blacksburg, VA, USA

Volume

6

Issue

3

fYear

2004

fDate

6/1/2004 12:00:00 AM

Firstpage

414

Lastpage

422

Abstract

This paper examines low power design techniques for discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuits applicable for low bit rate wireless video systems. The techniques include skipping DCT computation of low energy macroblocks, skipping IDCT computation of blocks with all coefficients equal to zero, using lower precision constant multipliers, gating the clock, and reducing transitions in the data path. The proposed DCT and IDCT circuits reduce power dissipation by, on average, 94% over baseline reference circuits.

Keywords

clocks; computational complexity; data compression; decoding; discrete cosine transforms; encoding; multiplying circuits; video codecs; DCT; H.263; IDCT; constant multipliers; data path; discrete cosine transform circuit; inverse discrete cosine transform circuits; low bit rate video codecs; low energy macroblocks; low power design techniques; power dissipation reduction; transition reduction; wireless video systems; Bit rate; Circuits; Clocks; Computational complexity; Decoding; Discrete cosine transforms; Motion estimation; Power dissipation; Quantization; Video codecs; DCT; Discrete cosine transform; H.26; IDCT; inverse discrete cosine transform; low power; video codec;

fLanguage

English

Journal_Title

Multimedia, IEEE Transactions on

Publisher

ieee

ISSN

1520-9210

Type

jour

DOI

10.1109/TMM.2004.827491

Filename

1298814