DocumentCode :
984502
Title :
Pseudorandom test-length analysis using differential solutions
Author :
Li, Dan ; Jone, Wen-Ben
Author_Institution :
Inst. of Astron. & Astrophys., Acad. Sinica, Taipei, Taiwan
Volume :
15
Issue :
7
fYear :
1996
fDate :
7/1/1996 12:00:00 AM
Firstpage :
815
Lastpage :
825
Abstract :
As the size of VLSI circuits increases, the use of random testing is becoming more common. One of the most important aspects of random testing is the determination of the test pattern length that guarantees a high confidence of fault detection. Generally, random test length is estimated by assuming that the set of test patterns applied is purely random. The assumption is not completely correct in applications where linear feedback shift registers (LFSR´s) are employed to generate input vectors. In this paper, we have developed a test (Markov) model which faithfully reflects the pseudorandom behavior of test patterns, and all detectable single stuck-at faults (instead of the worst single stuck-fault only) are considered. The required test length is then determined by solving differential equations to achieve the specified test confidence. Based on the test model, analysis is first dedicated to the two-fault case, results are then extended to the k-fault analysis where k⩾3. The test length thus determined is smaller than that derived based on the random pattern assumption, and test costs can be greatly reduced
Keywords :
Markov processes; VLSI; differential equations; digital integrated circuits; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; Markov model; VLSI circuits; differential equations; differential solutions; fault detection; k-fault analysis; linear feedback shift registers; pseudorandom test-length analysis; pseudorandom testing; single stuck-at faults; test confidence; test pattern length; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electrical fault detection; Extraterrestrial measurements; Fault detection; Integrated circuit modeling; Test pattern generators; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.503948
Filename :
503948
Link To Document :
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