• DocumentCode
    984518
  • Title

    Yield estimation model for VLSI artwork evaluation

  • Author

    Maly, Wojciech ; Deszczka, J.

  • Author_Institution
    Technical University of Warsaw, Instytut Technologii Elektronowej, Warszawa, Poland
  • Volume
    19
  • Issue
    6
  • fYear
    1983
  • Firstpage
    226
  • Lastpage
    227
  • Abstract
    In the letter a model which describes limitations of a manufacturing yield in terms of an IC artwork and a lithography characterisation is proposed. Density and distribution of diameters of defects present in the mask, as well as line-width fluctuations, are taken into account.
  • Keywords
    integrated circuit technology; large scale integration; monolithic integrated circuits; IC artwork; VLSI artwork evaluation; defect density; defect distribution; linewidth fluctuations; lithography characterisation; manufacturing yield; mask; yield estimation model;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19830156
  • Filename
    4247531
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=984518