Title :
Sub-fJ inverter analysis for GaAs VLSI
Author :
Togashi, Minoru ; Ino, M. ; Hirayama, Motoko
Author_Institution :
NTT, Musashino Electrical Communication Laboratory, Musashino, Japan
Abstract :
An E-D GaAs inverter in the low supply voltage region was analysed to obtain small energy operation. The optimum values for the switching FET threshold voltage and an average load current at a supply voltage VDD = 0.4 V are 0.2 V and half of an average on-current for the switching FET, respectively. Following this analytical design, 15-stage ring oscillators were fabricated and a minimum value for the product of inverter power dissipation and inverter switching time Pdistpd of 0.75 fJ was obtained.
Keywords :
III-V semiconductors; field effect integrated circuits; integrated logic circuits; large scale integration; semiconductor device models; 0.75 fJ invertor analysis; 15-stage ring oscillators; DCFL circuits; E-D GaAs inverter; GaAs VLSI; MESFET; average load current; logic circuits; low supply voltage region; model; power dissipation; small energy operation; switching FET threshold voltage; switching time;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19830159
