DocumentCode
984702
Title
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
Author
Li, James Chien-Mo
Author_Institution
Electr. Eng. Dept., Nat. Taiwan Univ., Taipei, Taiwan
Volume
13
Issue
6
fYear
2005
fDate
6/1/2005 12:00:00 AM
Firstpage
708
Lastpage
718
Abstract
A diagnosis technique to locate single stuck-at faults and multiple timing faults in scan chains is presented. This technique applies single excitation (SE) patterns, in which only one bit is flipped in the presence of multiple faults. With SE patterns, the problem of unknown values in scan chains is eliminated. The diagnosis result is therefore deterministic, not probabilistic. In addition to the first fault, this technique also diagnoses the remaining timing faults by applying multiple excitation patterns. Experiments on benchmark circuits show that average diagnosis resolutions are mostly less than five, even for the tenth fault in the scan chain.
Keywords
automatic test pattern generation; logic testing; timing; automatic test pattern generators; benchmark circuits; fault diagnosis; multiple excitation patterns; multiple timing faults; scan chains; stuck-at faults; Automatic test pattern generation; Benchmark testing; Circuit faults; Combinational circuits; Digital circuits; Fault diagnosis; Logic; Silicon; Test pattern generators; Timing; Automatic test pattern generators (ATPG); fault diagnosis; scan chain;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2005.848800
Filename
1458787
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