A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

Author

Caldwell, Trevor C. ; Johns, David A.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont.

Volume

41

Issue

7

fYear

2006

fDate

7/1/2006 12:00:00 AM

Firstpage

1578

Lastpage

1588

Abstract

This paper presents the first implementation results for a time-interleaved continuous-time DeltaSigma modulator. The derivation of the time-interleaved continuous-time DeltaSigma modulator from a discrete-time DeltaSigma modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass DeltaSigma modulator is designed in a 0.18-mum CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively

Keywords

CMOS integrated circuits; continuous time systems; delta-sigma modulation; discrete time systems; 0.18 micron; 10 MHz; 100 MHz; 101 mW; 103 mW; 20 MHz; 200 MHz; CMOS technology; DeltaSigma modulator; continuous-time modulator; discrete-time modulator; time-interleaved modulator; Bandwidth; CMOS technology; Clocks; Delay effects; Delta modulation; Digital filters; Digital modulation; Frequency; Pulse modulation; Sampling methods; Analog-to-digital conversion; continuous-time; delta-sigma modulation; oversampling; time-interleaving;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.873889

Filename

1644868