55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers

Author

Kurose, Daisuke ; Ito, Tomohiko ; Ueno, Takeshi ; Yamaji, Takafumi ; Itakura, Tetsuro

Author_Institution

Corp. Res. Dev. Center, Toshiba Corp., Kawasaki

Volume

41

Issue

7

fYear

2006

fDate

7/1/2006 12:00:00 AM

Firstpage

1589

Lastpage

1595

Abstract

A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples per second (MSPS). The 10-bit, 200-MSPS ADCs achieve maximum differential nonlinearity (DNL) of 0.66 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.00 LSB, a spurious-free dynamic range (SFDR) of 66.5 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 54.4 dB that corresponds to 8.7 effective number of bits (ENOB). The active area is 1.8 mm times 1.4 mm

Keywords

CMOS integrated circuits; analogue-digital conversion; radio receivers; 1.2 V; 1.4 mm; 1.8 mm; 10 bit; 55 mW; 90 nm; CMOS technology; analog-to-digital converters; pipeline ADC; power reduction technique; wireless receivers; Analog-digital conversion; CMOS technology; Differential amplifiers; Indium tin oxide; Mobile communication; Pipelines; Power amplifiers; Power dissipation; Switched capacitor circuits; Voltage; Amplifier sharing; analog-to-digital conversion; analog-to-digital converter (ADC); wireless receiver;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.873888

Filename

1644869