• DocumentCode
    986801
  • Title

    Fault effects in asynchronous sequential logic circuits

  • Author

    Shieh, M.-D. ; Wey, C.-L. ; Fisher, P.D.

  • Author_Institution
    Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
  • Volume
    140
  • Issue
    6
  • fYear
    1993
  • fDate
    11/1/1993 12:00:00 AM
  • Firstpage
    327
  • Lastpage
    332
  • Abstract
    The paper demonstrates the effects of single stuck-at faults in Huffman-model asynchronous sequential logic circuits (ASLCs). The fault effects include equivalent-state redundant faults, invalid-state redundant faults and state oscillations. Equivalent-state redundant faults in ASLCs may be generated by violation of the fundamental mode constraint noncritical races or delays. On the other hand, invalid-state redundant faults are caused either by the existence of invalid states, or by improperly assigning the "don\´t-care" terms. State oscillations are generally caused by the presence of critical races. Based on the fault effects, this paper presents a set of rules for synthesising oscillation-free ASLCs in the presence of faults. As far as synthesising testable ASLCs is concerned, the race-free UDC state assignment is much better than STT state assignment.
  • Keywords
    asynchronous sequential logic; delays; fault location; hazards and race conditions; integrated logic circuits; logic testing; state assignment; ASLCs; Huffman-model; STT state assignment; asynchronous sequential logic circuits; delays; don´t-care terms; equivalent-state redundant faults; fault effects; fundamental mode constraint noncritical races; invalid-state redundant faults; oscillation-free ASLCs; race-free UDC state assignment; single stuck-at faults; state oscillations;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings E
  • Publisher
    iet
  • ISSN
    0143-7062
  • Type

    jour

  • Filename
    249688