A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS

We present a low-jitter digital LC phase-locked loop (PLL) in a standard digital 130-nm CMOS technology, aiming at, but not limited to, clock multiplication in high-speed digital serial interface transceivers. The PLL features a fully digital core and a digitally controlled LC oscillator. The use of an integrated programmable coil enables triple-band operation in multi-GHz range (2.2, 3.4, and 4.6 GHz) on a die area as small as 0.21 mm². A new architecture is proposed which improves the authors´ previous work and allows to achieve an outstanding long-term jitter lower than 650 fs over the whole frequency range. The PLL consumes 13 mA of current at 1.5-V supply. Its performances compete favorably with the most advanced analog PLLs and are ahead of digital PLLs. Its digital nature makes it easily realizable in the mainstream digital CMOS technologies, robust against noise, and thus ideal for application as a low-jitter clock multiplying unit in digital intensive systems on chip.