Liquid-helium temperature hot-carrier degradation of Si p-channel MOSTs

Author

Simoen, E. ; Claeys, C.

Author_Institution

IMEC, Leuven, Belgium

Volume

140

Issue

6

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

431

Lastpage

436

Abstract

Results of a systematic study of the hot-carrier degradation of pMOSTs stressed at 4.2 K are reported. To a first approximation, the same shifts are observed as for room-temperature stress: a systematic increase in the drain current, both in linear operation and in saturation, caused by a positive shift of the threshold voltage. The transconductance is hardly affected for the devices and stress conditions studied. The substrate current is reduced in forward operation and increases for the reverse mode after stress. This degradation is partly removed by post-stress storage at room temperature. The results obtained point towards electron trapping in the oxide as the main degradation mechanism at 4.2 K in pMOSTs, although some interference with the substrate-related transient behaviour is observed

Keywords

electron traps; elemental semiconductors; hot carriers; insulated gate field effect transistors; semiconductor device testing; silicon; 4.2 K; Si; Si p-channel MOSTs; degradation mechanism; drain current; electron trapping; forward operation; hot-carrier degradation; linear operation; liquid-helium temperature; pMOSTs; post-stress storage; reverse mode; saturation; substrate current; substrate-related transient behaviour; threshold voltage;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings G

Publisher

iet

ISSN

0956-3768

Type

jour

Filename

249999