Title :
A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode
Author :
Sawada, Kazuhiro ; Sakurai, Takayasa ; Nogami, Kazutaka ; Sato, Katsuhiko ; Shirotori, Tsukasa ; Kakuma, M. ; Morita, Shigeru ; Kinugawa, Masaaki ; Asami, Tetsuya ; Narita, Kazuhito ; Matsunaga, Jun-Ichi ; Higuchi, Akira ; Isobe, Mitsuo ; Iizuka, Tetsuya
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
A 1-Mb (128K*8) pseudostatic RAM (PSRAM) is described. A novel feature of the RAM is the inclusion of a virtually static RAM (VSRAM) mode, while being fully compatible with a standard PSRAM. The RAM changes into the VSRAM mode when the RFSH pin is grounded, even in active cycles. The RAM can be used either as a fast PSRAM of 36-ns access time or as a convenient VSRAM of 66-ns access time. The typical operation current and data-retention current are 30 mA at 160-ns cycle time and 30 mu A, respectively. In order to achieve high-speed operation, low data-retention current, and high reliability, the RAM uses delay-time tunable design, a current-mirror timer, hot-carrier resistant circuits, and an optimized arbiter. These technologies are applicable to general advanced VLSIs.<>
Keywords :
CMOS integrated circuits; VLSI; integrated memory circuits; random-access storage; 1 Mbit; 160 ns; 30 mA; 30 muA; 36 ns; 66 ns; PSRAM; VLSI; VSRAM; current-mirror timer; cycle time; data-retention current; delay-time tunable design; high reliability; high-speed operation; hot-carrier resistant circuits; memory circuit; optimized arbiter; pseudostatic RAM; twin well CMOS technology; typical operation current; virtually static RAM mode; Computer peripherals; Delay effects; Design optimization; Microcomputers; Random access memory; Read-write memory; Reliability engineering; Semiconductor devices; Timing; Tunable circuits and devices;
Journal_Title :
Solid-State Circuits, IEEE Journal of
