• DocumentCode
    988361
  • Title

    On the parasitic gate capacitance of small-geometry MOSFETs

  • Author

    Kumar, M. Jagadesh ; Venkataraman, Vivek ; Gupta, Sumeet Kumar

  • Author_Institution
    Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India
  • Volume
    52
  • Issue
    7
  • fYear
    2005
  • fDate
    7/1/2005 12:00:00 AM
  • Firstpage
    1676
  • Lastpage
    1677
  • Abstract
    Parasitic capacitances in aggressively scaled-down MOSFETs play a major role in influencing the device performance. Accurate and simple models are required to predict the detrimental effect of the parasitic capacitances which often do not scale down with device dimensions.
  • Keywords
    MOSFET; capacitance; semiconductor device models; Kamchouci model; Suzuki model; edge capacitance; parasitic gate capacitance; small-geometry MOSFET; two-dimensional device simulator; Electrodes; Electron devices; Geometry; MOS devices; MOSFETs; Numerical models; Parasitic capacitance; Predictive models; Solid modeling; Two dimensional displays; Analytical model; MOSFETs; device scaling; parasitic capacitance;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2005.850630
  • Filename
    1459138
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=988361