DocumentCode :
988582
Title :
A heuristic for decomposition in multilevel logic optimization
Author :
Singh, Vinaya Kumar ; Diwan, Ajit A.
Author_Institution :
Silicon Automation Systems Ltd., Bangalore, India
Volume :
1
Issue :
4
fYear :
1993
Firstpage :
441
Lastpage :
445
Abstract :
A heuristic for finding common subexpressions of given Boolean functions based on Shannon-type factoring is proposed. This heuristic limits the search space considerably by applying a top-down approach in which synthesis of a Boolean network flows from the primary outputs to the primary inputs. The common subexpressions and their complements in N variables are extracted before common subexpressions and their complements in (N-1) variables. This decomposition of the network depends on a permutation of Boolean variables and has a polynomial complexity for restricted extraction of complements. A multilevel logic optimization system, MULTI, has been implemented using this heuristic. Good results on several benchmark circuits show its effectiveness.<>
Keywords :
Boolean functions; logic CAD; many-valued logics; optimisation; Boolean functions; MULTI; Shannon-type factoring; decomposition; heuristic; multilevel logic optimization; polynomial complexity; top-down approach; Automation; Boolean functions; Circuit synthesis; Computer science; Kernel; Logic; Network synthesis; Optimization methods; Polynomials; Silicon;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.250191
Filename :
250191
Link To Document :
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