The design and implementation of the Arithmetic Cube II, a VLSI signal processing system

Author

Owens, Robert Michael ; Kelliher, Thomas P. ; Irwin, Mary Jane ; Vishwanath, Mohan ; Bajwa, Raminder S. ; Yang, Wen-Lin

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

Volume

1

Issue

4

fYear

1993

Firstpage

491

Lastpage

502

Abstract

The Arithmetic Cube II, a high-performance signal processing system designed and built at Penn State University, is described. The architecture implements the so-called small-n algorithms, and is the first system making use of this approach to signal processing. The system is capable of computing a 1008-point complex-in complex-out discrete Fourier transform (DFT) in 3.54 ms. This high performance rate is achieved using very modest technology (2- mu CMOS). An overview of the small-n algorithms is provided. The architectural design and implementation of the system and the transform development environment are described, and results of operating the system are reported.<>

Keywords

CMOS integrated circuits; VLSI; add-on boards; fast Fourier transforms; signal processing equipment; 3.54 ms; Arithmetic Cube II; CMOS; Penn State University; VLSI signal processing system; complex-in complex-out discrete Fourier transform; performance rate; small-n algorithms; Arithmetic; Computer science; Discrete Fourier transforms; Pipelines; Process design; Signal design; Signal processing; Signal processing algorithms; Space technology; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.250197

Filename

250197