PREST: a system for logic partitioning and resynthesis for testability

Author

De, Kaushik ; Banerjee, Prithviraj

Author_Institution

Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA

Volume

1

Issue

4

fYear

1993

Firstpage

514

Lastpage

525

Abstract

The authors propose a heuristic procedure for partitioning a circuit into several blocks so that after the resynthesis of each block and subsequent reconnection there is a near-minimal number of redundant faults in the circuit. A probabilistic technique is used to estimate the size of a don´t care set, and the partitioning approach tries to reduce the don´t care size across the partitions. The approach, called PREST (for Partitioning and RESynthesis for Testability), has been applied on various MCNC and ISCAS benchmark circuits, and excellent results in terms of the size and testability of the synthesized circuit have been obtained.<>

Keywords

circuit analysis computing; logic CAD; logic testing; many-valued logics; probability; redundancy; PREST; heuristic procedure; logic partitioning; logic resynthesis; probabilistic technique; redundant faults; testability; Circuit faults; Circuit synthesis; Circuit testing; Logic circuits; Logic testing; Partitioning algorithms; Performance evaluation; Size measurement; System testing; Time measurement;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.250199

Filename

250199