Differential pass-transistor logic

Author

Pasternak, John H. ; Salama, C. Andre T

Author_Institution

Wafer Scale Integration Inc., Fremont, CA, USA

Volume

9

Issue

4

fYear

1993

fDate

7/1/1993 12:00:00 AM

Firstpage

23

Lastpage

28

Abstract

Differential pass-transistor logic (DPTL), which offers the noise immunity needed to use the unique switching properties of FETs in realizing switching network efficiencies, is discussed. CMOS DPTL offers significant power-delay product advantages over conventional CMOS logic for both 5-V and 3-V power supplies. These features are achieved by DPTL´s fewer and smaller parasitic capacitances, which are the result of significantly lower device counts combined with emphasized usage of minimum-size, n-channel pass-transistors. Substantial benefits are also obtained by using DPTL with depletion and enhancement/depletion GaAs MESFET technologies. Experiments show that GaAs DPTL offers substantial power-delay-product reductions over conventional GaAs realizations. Compared to CMOS DPTL, GaAs DPTL consumes less power at very high frequencies, a consequence of the electronic properties of GaAs and the smaller signal swings used in emitter/drain (E/D) DPTL.<>

Keywords

CMOS integrated circuits; Schottky gate field effect transistors; field effect integrated circuits; integrated logic circuits; 3 V; 5 V; CMOS logic; DPTL; FETs; GaAs; MESFET technologies; n-channel pass-transistors; noise immunity; parasitic capacitances; power-delay-product reductions; switching network efficiencies; Circuit noise; FETs; Logic circuits; Logic design; Logic devices; Logic functions; MOS devices; Switches; Switching circuits; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.250230

Filename

250230