Design of a rugged 60 V VDMOS transistor

Author

Xu, H.P.E. ; Trescases, O.P. ; Sun, I. S M ; Lee, D. ; Ng, W.T. ; Fukumoto, K. ; Ishikawa, A. ; Furukawa, Y. ; Imai, H. ; Naito, T. ; Sato, N. ; Tamura, S. ; Takasuka, K. ; Kohno, T.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON

Volume

1

Issue

5

fYear

2007

fDate

10/1/2007 12:00:00 AM

Firstpage

327

Lastpage

331

Abstract

Vertical double diffused MOSFET (VDMOS) is an established technology for high- current power-switching applications such as automotive circuits. The most serious failure mode is destructive damage during inductive switching, resulting from avalanche breakdown of the forward-blocking junction in the presence of high current flow. Improving the ruggedness of the device is achieved by enhancing its ability to absorb inductive energy under avalanche conditions. The purpose of the paper is to explore the possibility of improving the ruggedness of VDMOS through TCAD simulations. A p⁺-strip buried underneath an n⁺-source is proposed to suppress the turn-on of the parasitic bipolar transistor. VDMOS transistors with this design modification are expected to have higher ruggedness while maintaining its superior figure-of-merit.

Keywords

MOSFET; avalanche breakdown; power semiconductor devices; semiconductor device breakdown; semiconductor device models; switching circuits; TCAD; VDMOS transistor; avalanche breakdown; destructive damage; failure mode; forward-blocking junction; high current power-switching application; inductive switching; rugged transistor; vertical double diffused MOSFET;

fLanguage

English

Journal_Title

Circuits, Devices & Systems, IET

Publisher

iet

ISSN

1751-858X

Type

jour

DOI

10.1049/iet-cds:20070008

Filename

4389768