DocumentCode
988968
Title
Optimisation in resolving the buried line potential of VLSI circuits
Author
Barille, R.
Volume
29
Issue
5
fYear
1993
fDate
3/4/1993 12:00:00 AM
Firstpage
476
Lastpage
477
Abstract
During inspection or failure analysis of integrated circuits using an electron beam tester, an additional uncertainty linked to the operating conditions and structures under test must be considered to determine the potential of buried lines, apart from the systematic errors generally expected.
Keywords
VLSI; electron beam testing; failure analysis; inspection; integrated circuit testing; measurement errors; SEM operating conditions; VLSI circuits; buried line potential; coupling errors; electron beam tester; failure analysis; inspection; integrated circuits; surface voltage variation;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19930318
Filename
250278
Link To Document