Title :
New domino logic precharged by clock and data
Author :
Yuan, J.-R. ; Svensson, Christer ; Larsson, Peter
Author_Institution :
LSI Design Center, Linkoping Univ., Sweden
Abstract :
A clock-and-data precharged dynamic (CDPD) circuit technique in CMOS is presented. It gives a fast one-clock-cycle decision to multilevel logic and has small clock loads, low peak current, small area and low power-delay product. The technique is highly flexible in logic design. For the given example, a 324 bit binary-lookahead-carry chain, the speed improvement can be as high as 40-50% compared to the static circuit and 30% to the normal domino circuit arrangements while the area is reduced by 15-30%.
Keywords :
CMOS integrated circuits; carry logic; integrated logic circuits; logic design; many-valued logics; CMOS; binary-lookahead-carry chain; clock-and-data precharged dynamic circuit technique; domino logic; flexible logic design; low peak current; low power-delay product; multilevel logic; one-clock-cycle decision; small area; small clock load; speed improvement;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19931470
