• DocumentCode
    991003
  • Title

    Test function embedding algorithms with application to interconnected finite state machines

  • Author

    Kanjilal, Suman ; Chakradhar, Srimat T. ; Agrawal, Vishwani D.

  • Author_Institution
    Dept. of Comput. Sci., Rutgers Univ., New Brunswick, NJ, USA
  • Volume
    14
  • Issue
    9
  • fYear
    1995
  • fDate
    9/1/1995 12:00:00 AM
  • Firstpage
    1115
  • Lastpage
    1127
  • Abstract
    We present new algorithms for embedding test functions into the state diagram of a finite state machine. We first identify the cases where test functions can be embedded into the state diagram of the given object machine without using an extra input line. When such embedding is possible, our method finds it. In other cases, an extra input line must be added to the object machine to make the embedding possible. For the extra input case, we use partition theory and state variable dependencies in the object machine to obtain a mapping of the test machine states onto the object machine states. This mapping introduces a minimum number of extra state variable dependencies in the augmented machine as compared to the dependencies in the object machine. Experimental results on several MCNC benchmarks show that our method yields augmented machine implementations that have lower area than corresponding full scan designs. The test generation complexity for the augmented machine implementation is the same as that for a full scan design. We further consider the embedding of test functions into machines specified as an interconnection of finite state machines. We incorporate test functions into each component finite state machine such that the augmented interconnected machine has the same testability properties as the product machine with test function
  • Keywords
    automatic testing; finite state machines; logic partitioning; logic testing; sequential circuits; MCNC benchmarks; augmented machine implementations; interconnected finite state machines; partition theory; sequential circuit testing; state diagram; test function embedding algorithms; test generation complexity; testability properties; Application software; Automata; Circuit synthesis; Circuit testing; Hardware; Integrated circuit interconnections; Integrated circuit testing; Logic testing; National electric code; System testing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.406713
  • Filename
    406713