Accurate rounding scheme for the Newton-Raphson method using redundant binary representation

Author

Kabuo, Hideyuki ; Taniguchi, Takashi ; Miyoshi, Akira ; Yamashita, Hitoshi ; Urano, Miki ; Edamatsu, Hisakazu ; Kuninobu, Shigeo

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

43

Issue

1

fYear

1994

fDate

1/1/1994 12:00:00 AM

Firstpage

43

Lastpage

51

Abstract

Proposes a new algorithm of estimation and compensation of the error effect for rounding in the case of implementation of division and square root using the Newton-Raphson method. The authors analyze the error of the hardware system to confirm the condition of the implementation with respect to this algorithm. Next, they describe in detail how to compensate the error by using this algorithm. Finally, they show that the hardware components for this algorithm, the direct rounding mechanism in the recode circuit and the sticky digit generating circuit, can be realized simply by improving the redundant binary representation multiplier. The number of increasing cycles for this new algorithm is only one, and the rounding result using this algorithm satisfies IEEE Standard 754 rounding perfectly

Keywords

digital arithmetic; error analysis; Newton-Raphson method; error effect; recode circuit; redundant binary representation; redundant binary representation multiplier; rounding scheme; sticky digit generating circuit; Algorithm design and analysis; Approximation algorithms; Circuits; Equations; Error analysis; Error compensation; Floating-point arithmetic; Hardware; Helium; Newton method;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.250608

Filename

250608