• DocumentCode
    992332
  • Title

    Implementing Sparc in ECL

  • Author

    Brown, Emil W. ; Agrawal, Anant ; Creary, Trevor ; Klein, Michael F. ; Murata, David ; Petolino, Joseph

  • Author_Institution
    Sun Microsyst. Inc., Mountain View, CA, USA
  • Volume
    10
  • Issue
    1
  • fYear
    1990
  • Firstpage
    10
  • Lastpage
    22
  • Abstract
    A joint development project that implemented Sun Microsystems´ scalable processor architecture (Sparc) with Bipolar Integrated Technology´s bipolar emitter-coupled logic (ECL) is described. The authors review both ECL technology and the features of BIT´s ECL technique and discuss how board and cache considerations influenced the chip designs. Also discussed are the integer unit pipeline, system interface signals, and coprocessor interface. The chip set, now completed, performs at a level equal to large mainframe computers and approaches that of today´s supercomputers.<>
  • Keywords
    bipolar integrated circuits; computer architecture; emitter-coupled logic; microprocessor chips; ECL; Sparc; bipolar emitter-coupled logic; coprocessor interface; integer unit pipeline; scalable processor architecture; system interface signals; CMOS technology; Chip scale packaging; Circuits; Clocks; Costs; Microprocessors; Power dissipation; Sun; Very large scale integration; Workstations;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.46764
  • Filename
    46764
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=992332