• DocumentCode
    992737
  • Title

    Energy-efficient dual-port cache architecture with improved performances

  • Author

    Chen, X. ; Bajwa, H.

  • Author_Institution
    EE Dept., City Coll. of the City Univ. of New York, Grove Sch. Of Eng., NY
  • Volume
    43
  • Issue
    1
  • fYear
    2007
  • Firstpage
    12
  • Lastpage
    13
  • Abstract
    Low leakage current and area-efficient dual-port cache design, which uses isolation nodes and local sense amplifiers to facilitate dual-port accesses without duplicating the bit lines for the second port, is presented. Compared with conventional hardwired dual-port cache designs, the average bit line leakage current can be reduced by 50%
  • Keywords
    cache storage; leakage currents; low-power electronics; memory architecture; dual port cache; energy efficiency; isolation nodes; leakage current;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • Filename
    4068465
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=992737