DocumentCode
992887
Title
Arithmetic unit design for neural accelerators: cost performance issues
Author
Sammut, K.M. ; Jones, S.R.
Author_Institution
Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
Volume
44
Issue
10
fYear
1995
fDate
10/1/1995 12:00:00 AM
Firstpage
1256
Lastpage
1260
Abstract
Arithmetic unit design is a key issue when supporting the computational requirements of neural networks. However, there is little quantitative evidence from the study of existing neural accelerators to help choose between arithmetic constructs. This paper presents an assessment of the cost-performance trade-offs between arithmetic constructs for linear neural accelerators
Keywords
digital arithmetic; neural nets; arithmetic unit design; cost performance issues; cost-performance trade-offs; neural accelerators; Arithmetic; Circuits and systems; Clocks; Computer architecture; Computer networks; Costs; Linear accelerators; Logic testing; Neural networks; System testing;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.467702
Filename
467702
Link To Document