DocumentCode :
993019
Title :
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
Author :
Singh, Jaskirat ; Luo, Zhi-Quan ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN
Volume :
27
Issue :
2
fYear :
2008
Firstpage :
295
Lastpage :
308
Abstract :
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst case design scheme; however, it reduces the pessimism involved in traditional worst case methods by incorporating the effect of spatial correlations in the optimization procedure. The pessimism reduction is achieved by employing a bounded model for the parameter variations in the form of an uncertainty ellipsoid, which captures the spatial correlation information between the physical parameters. The use of the uncertainty ellipsoid, along with the assumption that the random variables corresponding to the varying parameters follow a multivariate Gaussian distribution, enables us to size the circuits for a specified timing yield. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the process variations. The resulting optimization problem is relaxed to a geometric program and is efficiently solved using convex optimization tools. The effectiveness of our robust gate sizing scheme is demonstrated by applying the optimization on the ISCAS´85 benchmark circuits and testing the optimized circuits by performing Monte Carlo simulations to model the process variations. Experimental results show that the timing yield of the robustly optimized circuits improves manifold over the traditional deterministically sized circuits. For the same transistor area, the circuits sized by our robust optimization approach have, on average, 12% fewer timing violations as compared to the gate sizing solutions that are obtained via the traditional deterministically based guard-banding method.
Keywords :
Gaussian distribution; Monte Carlo methods; circuit optimisation; convex programming; correlation methods; geometric programming; semiconductor process modelling; transistor circuits; ISCAS´85 benchmark circuits; Monte Carlo simulations; bounded model; circuit optimization scheme; convex optimization tools; effective channel lengths; geometric programming; modified delay constraints; multivariate Gaussian distribution; optimized circuit testing; physical parameters; posynomial delay model; process variations; spatial correlation; timing yield; transistor widths; uncertainty ellipsoid form; worst case design scheme; worst case gate sizing method; Benchmark testing; Circuit testing; Delay effects; Design optimization; Ellipsoids; Gaussian distribution; Random variables; Robustness; Timing; Uncertainty; Circuit optimization; timing; yield optimization;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2007.913391
Filename :
4391077
Link To Document :
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