Designing on-chip clock generators

With recent improvements in semiconductor technology, the speed of state-of-the-art microprocessors has doubled roughly every other year. At such high speed, distributing clock signals across the system and making sure every component in the system is synchronized become very important issues. It is shown that one way to solve the inter-chip clock synchronization problem is to use an on-chip phase-locked loop (PLL) for clock generation. The PLL can generate an on-chip clock that is phase-locked to the off-chip clock. Since the buffer to the PLL is lightly loaded, the delay through it is much smaller than the delay through a conventional clock buffer. As a result, inter-chip clock skew is substantially reduced. The functional blocks of a PLL clock generator, including phase detectors, charge pumps, loop filters, and voltage-controlled oscillators (VCOs) are described. Frequency synthesis in VCO-based PLLs and problems associated with designing and simulating PLLs are discussed.<>