• DocumentCode
    993645
  • Title

    Switched-capacitor delay circuit that is insensitive to capacitor mismatch and stray capacitance

  • Author

    Nagaraj, K.

  • Author_Institution
    Indian Telephone Industries, Digital Communication Group, Transmission R & D, Bangalore, India
  • Volume
    20
  • Issue
    16
  • fYear
    1984
  • Firstpage
    663
  • Lastpage
    664
  • Abstract
    A new switched-capacitor delay circuit which uses only a single amplifier and is insensitive to capacitor mismatch and stray capacitance is proposed. The insensitivity to capacitor mismatch permits the use of very small-valued capacitors so that the chip area can be reduced by device scaling as the feature sizes are reduced due to improvements in technology. Tapped analogue delay lines using such delay elements would be ideal for realising programmable and adaptive filters and equalisers in analogue LSI.
  • Keywords
    active networks; delay circuits; equalisers; large scale integration; switched capacitor networks; switched filters; analogue LSI; analogue delay lines; capacitor mismatch; chip area; device scaling; equalisers; feature sizes; filters; stray capacitance; switched-capacitor delay circuit;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19840454
  • Filename
    4248943