Capacitance of top leads metal - comparison between formula, simulation, and experiment

Author

Wright, Peter J. ; Shih, Yung-Che Albert

Author_Institution

Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA

Volume

12

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1897

Lastpage

1902

Abstract

The parasitic interconnection capacitance can significantly degrade the performance of an IC. In this paper, the parasitic capacitance of the top leads with a protective overcoat (PO) dielectric is modeled. For a nitride only PO, the nitride increases the line-to-line capacitance component by the average of the nitride and underlying oxide dielectric constants with a maximum error of 11% according to two-dimensional numerical simulations. If the oxide thickness of the PO is greater than 0.2 μm, then the line-to-ground component of capacitance will be within 10% of the value of a lead surrounded by oxide. The line-to-line component of capacitance can have an error of over 30% and a modification is required to reduce the error. Two modifications for the nitride/oxide PO are given; both increase the line-to-line capacitance by the fraction of nitride between the leads. The results of the modifications and simulation are compared to experiment. The two-dimensional simulations and formulas have a good fit to the experimental data

Keywords

VLSI; capacitance; digital simulation; integrated circuit technology; metallisation; monolithic integrated circuits; protective coatings; IC metallisation; dielectric constants; line-to-ground component; line-to-line capacitance component; maximum error; nitride dielectric; nitride/oxide structure; oxide dielectric; oxide thickness; parasitic capacitance; parasitic interconnection capacitance; protective overcoat dielectric; top leads metal; two-dimensional numerical simulations; Capacitance measurement; Circuit simulation; Dielectric constant; Integrated circuit interconnections; Integrated circuit modeling; Lead compounds; Numerical simulation; Parasitic capacitance; Protection; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.251153

Filename

251153