A delay-based model for circuit parallelism

Author

Bailey, Mary L.

Author_Institution

Dept. of Comput. Sci., Arizona Univ., Tucson, AZ, USA

Volume

12

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1903

Lastpage

1912

Abstract

A new formal model for variable-delay simulators is presented for comparing the effects of time base on circuit parallelism. This model more accurately reflects current simulation strategies than previous models. Using this new model the author shows that parallelism is not a nondecreasing function of time base. She bounds parallelism, however, by two functions that converge to the unit-delay parallelism as the time base increases, preserving the intuition that coarser timing models result in greater parallelism. In addition, the author corroborates the model predictions via an empirical study and discusses the impact of the results on synchronous and conservative asynchronous parallel simulations

Keywords

asynchronous sequential logic; digital simulation; logic CAD; asynchronous parallel simulations; circuit parallelism; delay-based model; empirical study; formal model; logic-level simulation; synchronous parallel simulations; time base; timing models; unit-delay parallelism; variable-delay simulators; Circuit simulation; Clocks; Computational modeling; Concurrent computing; Delay; Discrete event simulation; Parallel processing; Predictive models; Synchronization; Timing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.251154

Filename

251154