PMChip: an ASIC dedicated to pipelined read out and trigger systems

Author

Lai, A. ; Musa, L.

Author_Institution

Dipartimento di Fisica, Cagliari Univ., Italy

Volume

42

Issue

4

fYear

1995

fDate

8/1/1995 12:00:00 AM

Firstpage

812

Lastpage

819

Abstract

We describe a custom VLSI circuit, which is the main component of the read out system for some of the detectors of the NA48 experiment at the CERN SPS. Such a readout system is conceived to be completely dead time free and is based on a pipelined architecture. Our ASIC contains an 8 k circular memory, where data from ADC cards are stored continuously and can be retrieved after the time needed by the global trigger to make its decisions. It also contains a 256 locations output buffer for triggered data. The whole memory control logic has been integrated inside the ASIC. The VLSI approach allows us to implement a number of very useful features which could not be possible on a discrete component system

Keywords

CMOS memory circuits; VLSI; application specific integrated circuits; detector circuits; digital readout; digital signal processing chips; high energy physics instrumentation computing; nuclear electronics; pipeline processing; trigger circuits; 256 locations output buffer; ADC cards; ASIC; CERN SPS; CMOS; NA48 experiment; PMChip; circular memory; custom VLSI circuit; discrete component system; global trigger; memory control logic; pipelined architecture; pipelined read out; radiation detectors; trigger systems; triggered data; Application specific integrated circuits; Buffer storage; CMOS technology; Clocks; Data acquisition; Detectors; Frequency; Logic; Pipelines; Very large scale integration;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.467883

Filename

467883