A low-power, CMOS peak detect and hold circuit for nuclear pulse spectroscopy

A low-power CMOS peak detecting track and hold circuit optimized for nuclear pulse spectroscopy is presented. The circuit topology eliminates the need for a rectifying diode, reducing the effect of charge injection into the hold capacitor, incorporates a linear gate at the input to prevent pulse pileup, and uses dynamic bias control that minimizes both pedestal and droop. Both positive-going and negative-going pulses are accommodated using a complementary set of track and hold circuits. Full characterization of the design fabricated in 1.2 μm CMOS including dynamic range, integral nonlinearity, droop rate, pedestal, and power measurements is presented. The circuit operates with only 250 μw for input pulses with 7 μs peaking time. Power consumption was increased to 750 μw for driving off-chip and test system capacitances. Analysis and design approaches for optimization of operational characteristics are also discussed