A new approach to study electron and hole charge separation at the semiconductor-insulator interface

The charge transport and trapping properties of insulating films on semiconductors are related to reliability problems in MOSFETs and memory properties of nonvolatile memory devices. Physically based device models require delineation of electron and hole processes. Until recently, electron and hole charge separation at the semiconductor-insulator interface had been restricted to one gate bias polarity because of minority-carrier recombination-generation at the silicon surface. It is shown that a dual-channel transistor accomplishes electron and hole charge separation on the same microstructure for both gate polarities, obviating the need for complementary transistors and assumptions of identical dielectric and interface properties for a transistor pair. This approach is applied to the study of scaled dielectric oxide-nitride-oxide (ONO) memory devices, and their charge trapping characteristics are discussed