Title :
Understanding yield losses in logic circuits
Author :
Appello, Davide ; Fudoli, Alessandra ; Giarda, Katia ; Tancorre, Vincenzo ; Gizdarski, Emil ; Mathew, Ben
Author_Institution :
STM Electron., Cornaredo, Italy
Abstract :
Yield improvement requires understanding failures and identifying potential sources of yield loss. We focus on diagnosing random logic circuits and classifying faults. We introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers and correlation between the ATPG patterns and the tester failure reports.
Keywords :
automatic test pattern generation; failure analysis; fault simulation; integrated circuit yield; logic circuits; logic testing; system-on-chip; ATPG pattern; automatic test pattern generation; design automation tool; fault diagnosis; fault simulation; logic circuit yield loss; scan-based diagnosis flow; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Failure analysis; Fault detection; Fault diagnosis; Logic circuits; Logic testing; Pins;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2004.21
