• DocumentCode
    996070
  • Title

    Implicit deductive fault simulation for complex delay fault models

  • Author

    Deodhar, Jayant V. ; Tragoudas, Spyros

  • Author_Institution
    Texas Dev. Center, Intel Corp., Austin, TX, USA
  • Volume
    12
  • Issue
    6
  • fYear
    2004
  • fDate
    6/1/2004 12:00:00 AM
  • Firstpage
    636
  • Lastpage
    641
  • Abstract
    This paper introduces an implicit version of the well-known deductive fault simulation technique suitable to delay fault models with an exponential number of faults. The proposed method calculates the fault coverage by generating lists of entities for each line during a single topological circuit traversal. Each stored entity only contains a number and a subset of the test vectors. No delay faults are stored, and no special data structures are required. There are significant differences between the presented implicit method and fault coverage using deductive fault simulation. The method is shown to be effective for delay the path and segment delay fault models.
  • Keywords
    combinational circuits; delays; fault simulation; network topology; set theory; data structures; fault coverage; implicit deductive fault simulation; path delay fault models; segment delay fault model; subset; topological circuit traversal; Circuit faults; Circuit simulation; Circuit testing; Data structures; Delay effects; Dynamic programming; Electrical fault detection; Fault detection; Object detection; Robustness;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2004.827598
  • Filename
    1302146