Modeling subthreshold SOI logic for static timing analysis

Author

Valentian, Alexandre ; Thomas, Olivier ; Vladimirescu, Andrei ; Amara, Amara

Author_Institution

Inst. Superieur d´´Electronique de Paris, France

Volume

12

Issue

6

fYear

2004

fDate

6/1/2004 12:00:00 AM

Firstpage

662

Lastpage

669

Abstract

A simple, yet realistic physics-based model is introduced to describe the subthreshold drain current of a MOSFET taking into account the body- and drain-voltage dependencies, including the short channel effects. This model, verified by SPICE simulations, describes adequately the pseudotriode and pseudosaturation regions of MOS transistors operated below V/sub T/. It can be applied for predicting bulk- or partially depleted (PD) SOI CMOS circuit operation. Analytical expressions derived for the logic switching threshold and delay are applied to predict the performance of CMOS-SOI inverters.

Keywords

CMOS logic circuits; MOSFET; SPICE; integrated circuit modelling; low-power electronics; semiconductor device models; silicon-on-insulator; CMOS digital integrated circuits; MOSFET; SOI logic; SPICE simulations; analytical expressions; complementary metal-oxide-semiconductor; integrated circuit modelling; logic delay; logic switching; low-power electronics; metal-oxide-semiconductor field effect transistor; pseudosaturation regions; pseudotriode regions; short channel effect; silicon on insulator logic; simulation program with integrated circuit; static timing analysis; subthreshold drain current; CMOS logic circuits; Circuit simulation; Delay; MOSFET circuits; Performance analysis; Pulse inverters; SPICE; Semiconductor device modeling; Subthreshold current; Timing;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2004.827602

Filename

1302150