DocumentCode
996299
Title
Correlation of Prediction to On-Orbit SEU Performance for a Commercial 0.25-μm CMOS SRAM
Author
Hansen, D.L. ; Jobe, K. ; Whittington, J. ; Shoga, M. ; Sunderland, D.A.
Author_Institution
Boeing Satellite Dev. Center, Los Angeles
Volume
54
Issue
6
fYear
2007
Firstpage
2525
Lastpage
2533
Abstract
Boeing Satellite Development Center (SDC) geomoblie satellites have experienced a number of very large solar flares during their operational life. Comparison performance in a geostationary orbit to predictions based on heavy-ion ground testing for a digital signal processor (DSP) payload based on 0.25-mum CMOS, megagate-ASICs will be presented. Performance during flare peaks will be shown, and comparisons will be made between the response measured during each event, and some commonly used models. The results show that the careful technology selection and SEU mitigation techniques have enabled the spacecraft to operate through several periods of high radiation flux with no ill effects to the system.
Keywords
CMOS integrated circuits; SRAM chips; application specific integrated circuits; digital signal processing chips; radiation effects; CMOS SRAM; CMOS megagate-ASIC; SEU mitigation techniques; digital signal processor payload; geostationary orbit; heavy-ion ground testing; on-orbit SEU performance; size 0.25 mum; solar flares effects; spacecraft; CMOS process; CMOS technology; Digital signal processing; Digital signal processors; Extraterrestrial measurements; Payloads; Random access memory; Satellites; Semiconductor device modeling; Testing; Radiation; single event effects; solar particle events; space;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2007.908787
Filename
4395033
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