Title :
Voltage-sweep-circuit technique employing capacitance magnification
Author_Institution :
North East London Polytechnic, Dagenham, UK
Abstract :
A variation of the classic Blumlein¿Miller voltage-sweep-circuit technique employs capacitance magnification to minimise the magnitude of the timing capacitance required for a given sweep speed and charging current. In an illustrative circuit, a 10 pF capacitor is used in the generation of an 8 V amplitude sweep of about 8 ms duration.
Keywords :
time bases; 8 V amplitude sweep; capacitance magnification; timing capacitance; voltage sweep circuit technique;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19770092