• DocumentCode
    996463
  • Title

    Latch Design Techniques for Mitigating Single Event Upsets in 65 nm SOI Device Technology

  • Author

    KleinOsowski, A.J. ; Cannon, Ethan H. ; Gordon, Michael S. ; Heidel, David F. ; Oldiges, Phil ; Plettner, Cristina ; Rodbell, Kenneth P. ; Rose, Ronald D. ; Tang, Henry H K

  • Author_Institution
    IBM Austin Res. Lab., Austin, TX
  • Volume
    54
  • Issue
    6
  • fYear
    2007
  • Firstpage
    2021
  • Lastpage
    2027
  • Abstract
    This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments.
  • Keywords
    flip-flops; silicon-on-insulator; SOI device technology; latch design; master-slave flip-flop latches; silicon-on-insulator latches; single event upset mitigation; size 65 nm; Circuit topology; Error correction codes; Flip-flops; Inverters; Laboratories; Latches; Paper technology; Silicon on insulator technology; Single event upset; Threshold voltage; Alpha particle; modeling; radiation event; single event upset (SEU); soft error;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2007.909707
  • Filename
    4395047
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=996463